Processors, including microprocessors, digital signal processors and microcontrollers, operate by running software programs that are embodied in one or more series of instructions stored in a memory. The processors run the software by fetching the instructions from the series of instructions, decoding the instructions and executing them. The instructions themselves control the order in which the processor fetches and executes the instructions. For example, the order for fetching and executing each instruction may be inherent in the order of the instructions within the series. Alternatively, instructions such as branch instructions, conditional branch instructions, subroutine calls and other flow control instructions may cause instructions to be fetched and executed out of the inherent order of the instruction series.
When a processor fetches and executes instructions in the inherent order of the instruction series, the processor may execute the instructions very efficiently without wasting processor cycles to determine, for example, where the next instruction is. When flow control instructions are processed, one or more processor cycles may be wasted while the processor locates and fetches the next instruction required for execution.
In digital signal processing applications, and other mathematically intensive applications, programs frequently include repetitive operations embodied in repetitive instructions such as the multiply and accumulate (MAC) instruction. Repetitive instructions may be embodied within a program in various ways. For example, an instruction that is to be repeated may be literally repeated within the instruction series the required number of times. However, this is wasteful of program memory space. Alternatively, a conditional branch instruction may be included in an instruction sequence to define a repetitive software loop that includes the instruction for repetition and the number of times for repetition.
Software loops are helpful to keep the size of programs reasonable. However, software loops frequently result in wasted processor cycles while the processor resets it program counter to point from the last to the first instruction in the software loop.
Another technique to realize repeat loops is to provide a repeat instruction for causing a certain instruction to be executed a specified number of times. Repeat instructions have been provided on processors. However, repeat instructions have not conventionally permitted interrupts to be handled during repeat instruction processing thus significantly increasing interrupt latency. Moreover, some repeat instructions have been severely limited in terms of the number of times the instruction may be repeated. In addition, conventional repeat instructions waste processor cycles by continuously refetching the instruction for repetition within the series of instructions.
Accordingly, there is a need for a processor that implements repeat instruction processing in an efficient manner. There is a further need for a processor that implements a repeat instruction that permits the number of repetitions to be specified by the programmer. There is still a further need for repeat instruction processing that may be interrupted to handle exceptions that arise during the repeat instruction execution.
There is a further need for any such interrupts that arise during repeat instruction processing to be handled with a minimum loss in processor cycles and for nested interrupts to be processed during repeat instruction processing if necessary. There is still a further need for repeat loop processing to resume with a minimum loss in processor cycles after an interrupt is processed. There is still a further need to provide a simple solution to repeat instruction processing that minimizes the amount of logic required to implement the solution and thus the amount of space required on the processor to support the solution.